1. Field of the Invention
The present invention relates to data transfer in computer systems and more particularly to data transfer considerations between floppy disk controllers and direct memory access (DMA) controllers.
2. Description of the Prior Art
The personal computer industry is a dynamic and growing field that continues to evolve as new innovations occur. The driving force behind this innovation has been the increasing demand for faster and more powerful personal computers. Another major factor in the success of the personal computer industry has been that, in general, personal computer designers have strived to maintain compatibility between the newer systems and system components they are developing, and the older systems and system components that are currently on the market or in use. Historically, the personal computer has developed as a modular system incorporating an array of various components that each perform a particular task contributing to the functionality of the computer system. These various components have generally included random access memory, a microprocessor, and various coprocessors and support chips, among others. One method that has generally been used to increase computer speed has centered on increasing the performance of the various components which make up the computer, including the coprocessors and the various support chips which work in conjunction with the microprocessor and enable the computer to transfer data and process instructions. However, in this search for increased system component performance, personal computer chip designers have also generally attempted to ensure that previous generations of computer system components and software remain compatible with the latest computer system components they are developing.
An area of microprocessor systems design that has received attention in the pursuit of computer performance enhancement has been that of the data transfer rate between the computer's memory and the various I/O peripheral devices which are attached to the computer. In personal computers compatible with those previously manufactured and sold by International Business Machines Corp. (IBM), data transfers between memory and the various input/output (I/O) peripheral devices can be accomplished by means of a microprocessor support chip called the direct memory access (DMA) Controller. The DMA Controller allows data transfer between memory and the various I/O peripherals without the involvement of the microprocessor, thereby easing the workload of the microprocessor.
One of the standard DMA controllers that has generally been used in IBM compatible computers which utilize the Industry Standard Architecture (ISA) developed over the years is the Intel Corporation (Intel) 8237 DMA controller, which is described in the Microprocessor and Peripheral Handbook, Volume I, published by Intel. The 8237 DMA controller generally includes three data transfer modes. In single transfer mode, the DMA device is programmed to make one transfer only. In block transfer mode, the DMA I/O device is activated by a DMA request to continue making transfers during the service until a TC (terminal count) caused by the word count going to FFFFh, or an external end of process (EOP*), which signifies that the DMA service is completed, is encountered. In demand transfer mode the device is programmed to continue making transfers until a TC or external EOP* is encountered or until the DREQ signal goes inactive. Thus, in this mode transfers may continue until the I/O device has exhausted its data capacity Each of these modes generally includes a feature whereby the respective DMA channel can be programmed for an autoinitialization. During an autoinitialize, the original values of the current page, current address and current word count registers are automatically restored from the base page, address, and word count registers of that channel following an assertion of the terminal count (T-C) signal. Following an autoinitialize, the channel is ready to perform another DMA service without CPU intervention as soon as a valid DMA request is detected.
In conjunction with these data transfer modes, DMA devices capable of operating according to the Extended Industry Architecture (EISA) may generally use one of four cycle control sequences to transfer date between the DMA device and memory: ISA compatible cycles, Type "A" cycles, Type "B" cycles, or burst DMA cycles. ISA compatible or normal cycles are used by ISA DMA devices to transfer single bytes of data, and this cycle executes one transfer cycle in 8 BCLK periods. The remaining modes of delay may generally support 8-, 16- or 32-bit DMA devices. In Type "A" DMA cycles, transfers that do not require data size translation execute one cycle every 6 BCLK periods. In Type "B" DMA cycles, transfers that do not require data size translation execute one cycle every 4 BCLK periods. Burst DMA cycles can perform a sequence of transfers between EISA burst memory and the DMA device using 1 BCLK period per transfer.
The 8237 DMA controller generally includes three different types of transfers that are used in its data transfer modes, these being read, write, and verify. As the names suggest, read transfers move data from memory to an I/O device, while write transfers move data from an I/O device to memory. Verify transfers, however, are somewhat of an anomaly in that they are pseudo transfers. During verify transfers, the 8237 operates as if it were performing a read or write transfer, generating addresses and responding to the appropriate control signals. However, in a verify transfer, the memory and I/O control lines all remain inactive, and no data is actually sent or received by the DMA controller. Generally only the DMA acknowledge (DAK*) lines are active during a DMA verify transfer and the DMA controller counts the number of BCLK signals so that the appropriate DAK* line has a defined pulse width, this generally being 9 BCLK pulses long. However, if verify transfers are repeated during block or demand DMA requests, each additional pseudo transfer adds only 8 BCLKS, and the DAK* line remains at a low level for repeated transfers.
One I/O peripheral in particular that is involved in a large amount of data transfer with memory is the floppy disk drive of a computer system. In IBM compatible computers, the floppy disk drive of a computer system is generally controlled by a support chip called the floppy disk controller. One of the tasks of the floppy disk controller is to work in conjunction with the DMA controller to facilitate the transfer of data between the floppy disk drive of the computer system and the computer's memory. Generally, before there can be a transfer of data between the floppy disk controller and the DMA controller, a verify transfer is used to determine the type of floppy disk drive present within the system, this determination affecting the data rate that will be used in the upcoming transfer.
To determine the data rate, the systems software programs the DMA controller for the verify mode operation and issues a normal read command to the floppy disk controller. When the floppy disk controller has obtained the data from the floppy disk that is to be transferred to memory, it issues a DMA request (DREQ) signal to request the services of the DMA controller to coordinate the upcoming transfer. If the DMA controller is available, then it responds with a DMA acknowledge (DAK*) signal. However, since the DMA controller is in verify mode, the I/O control lines all remain inactive until the verify transfer is completed.
Previously, many IBM compatible computers were developed incorporating the .mu.PD765 floppy disk controller produced by NEC Electronics, Inc. The NEC .mu.PD765 is an IBM PC compatible floppy disk controller that only transfers one byte per data transfer cycle. When the DMA controller was ready to begin the process of transferring data between the floppy disk drive and memory, a verify cycle with the 765 floppy disk controller was performed to determine the proper data rate that was to be used. The 765 floppy disk controller circuitry was designed so that when it received the DAK signal, the data byte was transferred from the 765 floppy disk controller to the system data bus. Thus, the 765-based systems did not reference the I/O control lines in transferring data but used only the DAK signal.
The 765 floppy disk controller was generally limited in its data transfer capability, however, because it could only transfer one byte per data transfer cycle. This resulted in a low latency time so that the floppy disk controller had to be accessed by the DMA controller a short time after it had requested access or data errors would occur. This low latency or response time became a problem with more complex computer systems. Therefore Intel Corporation (Intel), a major manufacturer of computer chips and microprocessors for IBM compatible computers, developed a new floppy disk controller called the 82077, which is capable of transferring data in a burst mode from a first-in, first-out (FIFO) register. The FIFO is used preferably to buffer data being received by the floppy disk controller from the floppy disk drive so that the latency time can be increased. Additionally, the FIFO allows block transfers to be made with the floppy disk controller, improving data transfer rates Generally, the FIFO is 16 bytes in size, and all data transfers involving the floppy disk controller pass through the FIFO after FIFO mode operation is enabled. For further details on the 82077, please refer to the Microprocessor and Peripheral Handbook, Volume II, published by Intel.
Like the NEC 765 floppy disk controller, the Intel 82077 floppy disk controller is generally required because of software compatibility concerns to operate with verify cycles in order to determine the correct data rate of the upcoming data transfer. However, the 82077 has been designed such that it generally receives an I/O control signal referred to as IORC* to signify that it may clock data out from its FIFO. Thus, each pulse of the IORC* signal results in the transfer of one byte. However, the IORC* signal is not activated by the DMA controller when verify operations are occurring. Thus, the data is not removed from the FIFO and overrun errors can occur as more data is received from the floppy disk drive. The DAK signal cannot be used to clock out data from the FIFO because it only changes state once per DMA request, not as many times as the IORC* signal may toggle during burst or demand transfers.